1. Field of the Invention
The present invention relates to a three-dimensional semiconductor device in which a plurality of semiconductor circuit chips are stacked, and more particularly to a three-dimensional semiconductor memory device in which memory cells are formed on stacked semiconductor circuit chips.
2. Description of the Related Art
In recent years, improvements in integration density resulting from the miniaturization of semiconductor integrated circuits have resulted in great advances in the storage capacity in DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory). However, because there are limits to miniaturization of semiconductors, new technologies are being sought to achieve further advances in integration density. Three-dimensional semiconductor devices (stacked semiconductor devices) in which semiconductor circuit chips are stacked have been proposed as one such technology. A method of stacking semiconductor circuit chips to realize large-scale integrated circuits without changing the chip surface area is described in, for example, Japanese Patent Laid-Open Publication No. H04-196263. In this method, memory circuits are integrated on separate chips that are stacked on the main body of semiconductor integrated circuits. In addition, a multilayered memory configuration in which memory cell arrays are multilayered to achieve a further increase in capacity is described in, for example, Japanese Patent Laid-Open Publication No. 2002-026283.
Multilayering of semiconductor circuit chips necessitates interchip interconnections in addition to conventional in-plane interconnections on chip surfaces. Through-vias that pass through chips have been used as interchip interconnections to achieve higher interconnection density. A method in which a silicon chip is thinned to 50 μm, square holes measuring 10 μm on a side are formed in the chip, and the holes then filled with metal to form through-vias for interchip interconnections is described in K. Takahashi et al. in the Japanese Journal of Applied Physics (40, p. 3032 (2001)). By means of these through-vias, interchip interconnections can be arranged two-dimensionally within the chip surface to enable a configuration with several hundred interchip interconnections.
However, in contrast with in-plane interconnections having a thickness of 1 μm or less, through-vias require a thickness of at least 10 μm. This requirement stems from both the difficulty of accurately forming through-holes in a chip with a high aspect ratio due to the restrictions of through-via processing, and the necessity for through-vias that are considerably larger than several μm to achieve the interchip alignment accuracy that is necessary for aligning the positions of through-vias between stacked chips.
Because the cross-sectional shape of through-vias is larger than that of in-plane interconnections, the electrical characteristics of the two types of interconnections differ greatly. Interconnection resistance being inversely proportional to the cross-sectional area of the interconnection, the interconnection resistance of through-vias, which have a large cross section, is lower than that of in-plane interconnections and the conditions for interchip interconnection are therefore more advantageous. However, the amount of parasitic capacitance between an interconnection and a silicon substrate is proportional to the area over which the interconnection confronts the substrate. A through-via is therefore less advantageous than an in-plane interconnection because a through-via interconnection is not only surrounded by the silicon substrate chip, but the through-via has a greater interconnection cross-sectional area and a longer perimeter. For example, if a through-via with a circular profile having a cross-sectional diameter of 20 μm passes through a silicon substrate that is interposed between insulating films each having a thickness of 250 nm and the thickness of the substrate is 50 μm, i.e., the length of the through-via is 50 μm, the parasitic capacitance will be 0.45 pF. The parasitic capacitance of an in-plane interconnection that is in common use is approximately 0.2 pF per 1 mm, meaning that the parasitic capacitance of 0.45 pF of a through-via is equivalent to the parasitic capacitance of in-plane interconnection that is approximately 2 mm long.
In a three-dimensional semiconductor, in-plane interconnections and interchip interconnections extend three-dimensionally to distribute signals to circuits that cover the surfaces of the stacked semiconductor circuit chips. The power consumption that is required for charging and discharging interconnections with each signal transmission increases proportionally with the interconnection capacitance. Accordingly, to reduce power consumption, the interconnection capacitance must be reduced to the minimum.
As an example, the following explanation regards a case as shown in FIG. 1, in which semiconductor circuit chips 30 having a chip size of 20 mm in width and 10 mm in length are stacked in eight layers on interface chip 20, which is a chip for realizing an interface for transmitting signals between semiconductor circuit chips 30 and the outside, signals are distributed to sub-circuit regions 5 that are produced by dividing the surface of each semiconductor circuit chip 30 by eight horizontally and 4 vertically for a total of 32 sites, and through-vias are used for interchip interconnections. Sub-circuit regions 5 described here are banks in which the memory regions have been divided for the purpose of interleaving or divided regions of a memory in which word lines and bit lines are each divided and separate decoders are arranged. Explanation here regards a case in which the chip thickness is 50 μm.
Methods for distributing signals from input/output buffer 10 that is in the corner of lower-most interface chip 20 to all semiconductor circuit chips 30 that are stacked above include the in-plane interconnection type and the interchip interconnection type as shown in FIGS. 2A and 2B. As shown in FIG. 2A, the in-plane interconnection type employs only one interchip interconnection 50 between chips, signals being distributed by in-plane interconnection 40 of the prior art on the surface of each semiconductor circuit chip 30. As shown in FIG. 2B, in the interchip interconnection type, in-plane interconnections 40 are distributed two-dimensionally on interface chip 20, following which 32 interchip interconnections 50 are used to distribute signals vertically to all semiconductor circuit chips 30.
In the in-plane interconnection type that is shown in FIG. 2A, signal transmission is realized by one interchip interconnection 50 between chips, but in the interchip interconnection type that is shown in FIG. 2B, interchip interconnections 50 for signal transmission between semiconductor circuit chips 30 are provided for each of sub-circuit regions 5 having the same position on semiconductor circuit chips 30.
FIG. 3 shows a comparison of the total three-dimensional interconnection capacitance of these two methods that results from changes in the capacitance of through-vias. The calculation of capacitance is based on the assumption that the capacitance of an in-plane interconnection is 0.2 pF per millimeter. In addition, the through-via capacitance on the horizontal axis of FIG. 3 shows the capacitance of one interconnection of one chip (50 μm long). Reference to FIG. 3 reveals that, in the in-plane interconnection type, despite the low degree of dependence on through-via capacitance, the provision of in-plane interconnections on the surface of each semiconductor circuit chip results in a high level of the total three-dimensional interconnection capacitance even when the through-via capacitance is low. On the other hand, dependence on the amount of through-via capacitance is high in the interchip interconnection type, and the total three-dimensional interconnection capacitance therefore increases as the through-via capacitance increases. As result, the interchip interconnection type enables a lower level of total three-dimensional interconnection capacitance than the in-plane interconnection type when the through-via capacitance is low, but when the through-via capacitance exceeds 0.5 pF, the levels of total three-dimensional interconnection capacitance reverse and the interchip interconnection type produces the higher level of total three-dimensional interconnection capacitance. In addition, an increase in the number of sites of in-plane distribution, i.e., an increase in the number of interchip interconnections, results in a further increase in the dependency on the through-via capacitance in the interchip interconnection type.
In a three-dimensional semiconductor device in which a plurality of chips are stacked and three-dimensional interconnections are implemented, the lowest possible capacitance of the interchip interconnections is demanded, but as described in the foregoing explanation, the through-vias that are used in interchip interconnections have a large profile, and reducing the capacitance of the through-via themselves is problematic. Reducing the total three-dimensional interconnection capacitance is therefore problematic in the interchip interconnection type, and because interconnection capacitance resulting from in-plane interconnections increases even in the in-plane interconnection type, total three-dimensional interconnection capacitance is extremely difficult to reduce beyond a certain level.